In present semiconductor technology, CMOS devices, such as NFETs or PFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, PFETs are typically designed with larger widths in order to balance pull-up currents against the NFET pull-down currents and achieve uniform circuit switching. NFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, PFETs formed on a (110) surface will exhibit significantly higher drive currents than PFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces. The electron mobility degradation on a (110) Si surface is shown, for example, in FIG. 1. In FIG. 1, the solid line represents electron mobility, while the dashed line represents hole mobility.
As can be deduced from the above discussion and FIG. 1, the (110) Si surface is optimal for PFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for NFET devices. Instead, the (100) Si surface is optimal for NFET devices since that crystal orientation favors electron mobility.
In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a substrate having different crystal orientations that provide optimal performance for a specific device. That is, there is an overwhelming need to create a substrate which allows one type of device, such as, for example, a PFET, to be formed on a certain crystallographic surface, e.g., a (110) surface, while forming another type of device, such as, for example, an NFET, on another crystallographic surface, e.g., a (100) surface.